1. Field of the Invention
This invention relates to a method for detecting a position of consecutive bits set to a predetermined code wherein, from a signal constituted of a plurality of words, the position in the signal is detected at which bits set to a predetermined code occur consecutively by a length not less than the bit length constituting a single word.
2. Description of the Prior Art
In general, digital signals representing images, or the like, are composed of enormous amounts of information. Therefore, in general, before the digital signals are stored on a storage medium or are transmitted between signal processing apparatuses, they are compressed. The digital signals are compressed by restricting redundancy of the signals by the utilization of the characteristics that the signal components representing the neighboring picture elements of a single image have a high correlation to each other. During the compression of a digital signal, a predetermined number of consecutive bits, which have been set to a predetermined code, are often inserted into the top of each set of signal components of the digital signal, which has been compressed, in order to indicate the location of the top of each set. The predetermined number is not less than the number of bits constituting a single word. For example, in cases where a digital signal was detected from an image by scanning the image along a plurality of main scanning lines, a series of signal components of a compressed digital signal, which represent picture elements in the image located along a single main scanning line, are taken as one set. Thereafter, a predetermined number of bits, which number is not less than the number of bits constituting a single word and is, for example, at least 17, are set to a predetermined code (i.e. 0 or 1) and consecutively inserted into the top of each set of signal components.
The number of consecutive bits will herein be often referred to as the bit length.
FIG. 4 is a block diagram showing an example of a series of processes for compressing and recompressing a signal.
With reference to FIG. 4, a digital signal S1, which has been generated by, for example, an image read-out apparatus (not shown) and is made up of a series of signal components representing an image, is fed into a signal compressor 1. In the image read-out apparatus, the digital signal S1 is detected from the image by scanning the image along a plurality of main scanning lines. In the signal compressor 1, a series of signal components of the digital signal S1, which represent picture elements in the image located along each main scanning line, are taken as one set, and signal compression is carried out on each set of signal components. Also, 17 consecutive bits, which have been set to 0, are inserted into the top of each set of signal components. In this manner, a compressed image signal S2 is generated. The compressed image signal S2 is then stored in an image filing apparatus 2, which stores (files) a plurality of compressed digital signals representing images. When necessary, the compressed image signal S2 is read from the image filing apparatus 2 and fed into a zero length detecting circuit 3 and a signal recompressor 4. The zero length detecting circuit 3 detects at least 17 consecutive bits, which have been set to 0 and are present in the compressed image signal S2, and thereby finds the position of the top of each set of signal components of the digital signal representing picture elements located along a single main scanning line. The zero length detecting circuit 3 feeds information about the position of the top of each set of signal components into the signal recompressor 4. The signal recompressor 4 receives the compressed image signal S2 from the image filing apparatus 2 and recompresses it in accordance with the information, which represents the position of the top of each set of signal components and is received from the zero length detecting circuit 3. The signal recompressor 4 thus generates an recompressed image signal S3, which is approximately identical with the original digital signal S1. (In cases where an irreversible compression process was carried out on the original digital signal S1, the recompressed image signal S3 becomes slightly different from the original digital signal S1.) The recompressed image signal S3 is fed into a CRT display device (not shown), which reproduces a visible image from the recompressed image signal S3 and displays it.
In the example described above, during the compression of a digital signal, a predetermined number of consecutive bits, which have been set to a predetermined code (0), are inserted into the top of each set of signal components of the digital signal, which has been compressed, in order to indicate the location of the top of each set. Also when, for example, a digital signal is transmitted between signal processing apparatuses, bits which have been set to, e.g., 0 are consecutively inserted by a predetermined length into the top of a group of signal components of the digital signal in order to indicate the location of the top of the group.
In cases where, for example, a digital signal is subjected to compression and extension processing or is transmitted between signal processing apparatuses, it is necessary to detect with, for example, a zero length detecting circuit whether bits which have been set to, e.g., 0 occur or do not occur consecutively at least by a predetermined length in a digital signal.
FIG. 5 is a diagram showing an example of a conventional zero length detecting circuit, which is employed to detect whether bits which have been set to 0 occur or do not occur consecutively at least by a predetermined length in a digital signal.
With reference to FIG. 5, a shift register 5 is constituted of a parallel-input, serial-output type 16-bit shift register. A digital signal S4 constituted of a plurality of words, such as the compressed image signal S2 shown in FIG. 4, is sequentially fed in units of a single work into the shift register 5. In this example, one word is constituted of 16 bits. Each time a single word is fed into the shift register 5, 16 pulses of a clock signal CL are fed into the shift register 5. In this manner, the data in the shift register 5 is serially fed into a shift register 6. The shift register 6 is of the serial-input, parallel-output type and has a bit length, which is determined in accordance with how many consecutive bits set to 0 should at least be detected. In cases where all of the bits in the shift register 6 become 0, a pulse signal shown in FIG. 4 is generated and fed out from a gate circuit 7, which is connected to the parallel output terminals of the shift register 6. In this manner, it can be detected that the bits which have been set to 0 occur consecutively at least by the predetermined length in the digital signal S4.
With the conventional zero length detecting circuit described above, the parallel signal components received in units of a single word are transformed into a serial signal. Therefore, a long time is taken for the zero length to be detected. As a result, the speed, with which a series of processes, .such as signal extension, are carried out, cannot be kept high.